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HD151BF854
2.5 V PLL Clock Buffer for DDR Application
REJ03D0809-0500 (Previous: ADE-205-696D) Rev.5.00 Apr 07, 2006
Description
The HD151BF854 is a high-performance, low-skew, low-jitter, PLL clock buffer. It is specifically designed for use with DDR (Double Data Rate) PC motherboard application.
Features
* * * * * *
*
Designed for DDR200/266/333/400 PC mother board clock buffering Supports 60 MHz to 210 MHz operation range Distributes one to six differential clock outputs pairs Spread spectrum clock compatible External feedback pin (FBIN) is used to synchronize the outputs to the clock input Supports 2.5 V analog supply voltage (AVDD), and 2.5 V VDD Ordering Information
Part Name Package Type SSOP-28 pin Package Code (Previous Code) PRSP0028JA-A (FP-28DSAV) SS Package Abbreviation Taping Abbreviation (Quantity) EL (1,000 pcs / Reel)
HD151BF854SSEL
Key Specifications
* Supply voltages: VDD = AVDD = 2.5 V0.2 V * Output clock cycle to cycle jitter = 75 ps * Output clock pin to pin skew = 150 ps
Function Table
Inputs AVDD GND GND 2.5 V (typ.) 2.5 V (typ.) H: High level L: Low level CLK L H L H Yn L H L H Outputs Yn H L H L FBOUT L H L H PLL Bypass / Off Bypass / Off Running Running
Rev.5.00 Apr 07, 2006 page 1 of 7
HD151BF854
Pin Arrangement
Y0 1 Y0 2 VDD 3 Y1 4 Y1 5 GND 6 NC 7 CLKIN 8 NC 9 AVDD 10 AGND 11 VDD 12 Y2 13 Y2 14
28 GND 27 Y5 26 Y5 25 Y4 24 Y4 23 VDD 22 NC 21 NC 20 FBIN 19 FBOUT 18 NC 17 Y3 16 Y3 15 GND
(Top view)
Pin Functions
Pin name AGND AVDD No. 11 10 Type Ground Power Description Analog ground. AGND provides the ground reference for the analog circuitry. Analog power supply. AVDD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Clock input. CLKIN provides the clock signal to be distributed by the HD151BF854 clock buffer. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLKIN and FBIN so that there is nominally zero phase error between CLKIN and FBIN. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Ground Power supply Clock outputs. (+Clock) These outputs provide low-skew copies of CLK. Bar clock outputs. (-Clock) These outputs provide low-skew copies of CLK. Don't connect any VDD or GND.
CLKIN
8
Input
FBIN
20
Input
FBOUT
19
Output
GND VDD Y Y NC
6, 15, 28 3, 12, 23 2, 4, 13, 17, 24, 26 1, 5, 14, 16, 25, 27
Ground Power Output Output
7, 9, 18, 21, NC 22
Rev.5.00 Apr 07, 2006 page 2 of 7
HD151BF854
Logic Diagram
2 1
Y0 Y0
AVDD
10
Test Logic
4 5
Y1 Y1
13 14
Y2
Y2
17 16
Y3 Y3
24 25
Y4 Y4
CLKIN
8
PLL
26 27
Y5 Y5
FBIN
20
19
FBOUT
Note: All inputs and outputs are associated with VDDQ = 2.5 V.
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage *1 Input clamp current Output clamp current Continuous output current Maximum power dissipation at Ta = 55C (in still air) Storage temperature Notes: Symbol VDD VIC VI VO IIK IOK IO Ratings -0.5 to 3.6 -0.5 to 3.6 -0.5 to VDD+0.5 -0.5 to VDD+0.5 -50 -50 50 0.7 Tstg -65 to +150 Unit V V V V mA mA mA W Conditions CLKIN
VI < 0 VO < 0 VO = 0 to VDD
C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Rev.5.00 Apr 07, 2006 page 3 of 7
HD151BF854
Recommended Operating Conditions
Item Supply voltage Output supply voltage DC input signal voltage High level input voltage High level input voltage Low level input voltage Output differential cross point voltage Output current Input clock slew rate Operating temperature Symbol AVDD VDD VIH VIH VIL VOX IOH IOL SR Ta Min 2.3 2.3 -0.3 1.7 1.7 -0.3 0.5xVDD -0.2 -- -- 1 0 Typ 2.5 2.5 -- -- -- -- -- -- -- -- -- Max 2.7 2.7 VDD+0.3 3.6 VDD+0.3 0.7 0.5xVDD +0.2 -12 12 -- 70 Unit V V V V V V V mA V/ns Conditions
All pins CLKIN FBIN CLKIN, FBIN
C
Note: Unused inputs must be held high or low to prevent them from floating.
Electrical Characteristics
Item Input clamp voltage (All inputs) Output voltage Symbol VIK VOH VOL Input current Analog supply current Dynamic supply current Input capacitance*2 Delta input capacitance*2 II AICC DICC CI CDi Min --
VDD-0.2
Typ *1 -- -- -- -- -- -- -- 250 -- --
Max -1.2 -- VDD 0.2 0.6 10 12 300 3.5 0.25
Unit V V
Test Conditions II = -18 mA, VDD = 2.3 V IOH = -100 A, VDD = 2.3 to 2.7 V IOH = -12 mA, VDD = 2.3 V IOL = 100 A, VDD = 2.3 to 2.7 V IOL = 12 mA, VDD = 2.3 V VI = 0 V or 2.7 V, VDD = 2.7 V, CLKIN, FBIN VDD = AVDD = 2.7 V, 170 MHz VDD = AVDD = 2.7 V, 170 MHz, All Yn, Yn, = open CLKIN and FBIN
1.7 -- -- -10 -- -- 2.5 -0.25
A mA mA pF pF
Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. 2. Target of design, not 100% tested in production.
Rev.5.00 Apr 07, 2006 page 4 of 7
HD151BF854
Switching Characteristics
Ta = 25C, VDD = AVDD = 2.5V
Min Typ Max Unit Test Conditions & Notes Period jitter -- |75| -- ps *7, 8 Half period jitter -- |120| -- ps *8 Cycle to cycle jitter -- |75| -- ps Static phase offset -- |150| -- ps *4, 5 Output clock skew -- 150 -- ps Operating clock frequency 60 -- 210 MHz *1, 2 Application clock frequency 80 166 210 MHz *1, 3 Slew rate 1.0 -- 2.0 V/ns 20% to 80% Stabilization time -- -- 0.1 ms *6 Notes: Target of design, not 100% tested in production. 1. The PLL must be able to handle spread spectrum induced skew. (the specification for this frequency modulation can be found in the latest Intel PC100 Registered DIMM specification) 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4. Assumes equal wire length and loading on the clock output and feedback path. 5. Static phase offset does not include jitter. 6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of it's feedback signal to it's reference signal after power on. 7. Period jitter defines the largest variation in clock period, around a nominal clock period. 8. Period jitter and half period jitter are separate specifications that must be met independently of each other. Item Symbol tPER tHPER tCC tsPE tsk fCLK(O) fCLK(A)
Rev.5.00 Apr 07, 2006 page 5 of 7
HD151BF854
Yn
Zo = 60 RT = 120 C = 14 pF
*1
Yn
Zo = 60
*1
C = 14 pF
Note: 1. SDRAM Cin 3.5 pF x4
Figure 1 Clock outputs test circuit
Yn Yn tcycle n
tcycle n+1
t CC = (tcycle n) - (tcycle n+1)
Figure 2 Cycle to cycle jitter
Yx Yx Yy Yy tsk
Figure 3 Output clock skew (Differential clock output)
Rev.5.00 Apr 07, 2006 page 6 of 7
HD151BF854
Package Dimensions
JEITA Package Code P-SSOP28-5.3x10.2-0.65 RENESAS Code PRSP0028JA-A Previous Code FP-28DSA/FP-28DSAV MASS[Typ.] 0.255g
*1
D
F 15
28
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
b1
c1
Terminal cross section
c
Index mark
*2
E
Reference Dimension in Millimeters Symbol
1
Z
e
*3
14
bp
x
M
L1
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.20 10.50 5.30
0.00 0.10 0.20 2.10 0.24 0.32 0.40 0.30 0.17 0.22 0.27 0.20 0 8 7.70 7.90 8.10 0.65 0.13 0.10 1.025 0.45 0.60 0.75 1.30
Rev.5.00 Apr 07, 2006 page 7 of 7
A
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